1. Field
The embodiment(s) relate to an optical receiver, a signal generating circuit, and a light receiving method.
2. Description of the Related Art
FIG. 16 illustrates a configuration example of a general optical receiver used in an optical communication system in related art. Referring to FIG. 16, the optical receiver includes a positive-intrinsic-negative photodiode (PIN-PD) 11, a transimpedance amplifier (TIA) 12, a limiting amplifier (LIA) 13, and a decision circuit (DEC) 14.
The PIN-PD 11 converts an optical signal that is received into an electrical signal and outputs the electrical signal. The TIA 12 performs current-voltage conversion. The LIA 13 amplifies the electrical signal resulting from the conversion and supplies the amplified electrical signal to the DEC 14. The DEC 14 generates a data signal in synchronization with a clock signal.
FIG. 17 illustrates a configuration example of another general optical receiver. Referring to FIG. 17, the optical receiver has a configuration in which the LIA 13 in FIG. 16 is replaced with an automatic gain control amplifier (AGC) 15.
The AGC 15 amplifies an electrical signal output from the TIA 12 and supplies the amplified electrical signal to the DEC 14. The gain in the AGC 15 is controlled so that the signal to be supplied to the DEC 14 has a constant level.
In optical receivers in the related art, an optical signal that is input is usually processed as a serial signal before the optical signal reaches the DEC 14. In addition, in order to realize a sufficient performance in response to the input optical signal having a low power, the optical receiver includes electrical amplifiers, such as the TIA 12 and the LIA 13 or the AGC 15, having higher gains.
FIG. 18 illustrates a configuration example of a coherent digital optical receiver in the related art. A modulation method, such as a dual polarization-differential quadrature phase shift keying (DP-DQPSK) or a dual polarization-quadrature phase shift keying (DP-QPSK), is adopted in such a coherent digital optical receiver in order to realize high-speed optical transmission.
Referring to FIG. 18, the digital optical receiver includes an optical hybrid 21, PIN-PDs 22-1 to 22-4, TIAs 23-1 to 23-4, AGCs 24-1 to 24-4, analog-to-digital converters (ADCs) 25-1 to 25-4, and digital signal processors (DSPs) 26-1 to 26-4. The PIN-PDs 22-1 to 22-4, the TIAs 23-1 to 23-4, the AGCs 24-1 to 24-4, the ADCs 25-1 to 25-4, and DSPs 26-1 to 26-4 are collectively referred to as a PIN-PD 22, a TIA 23, an AGC 24, an ADC 25, and a DSP 26, respectively. The same applies to elements described below.
An optical signal including two polarizations and a light oscillated from local oscillator are input into the optical hybrid 21. The optical hybrid 21 mixes the signal light with the local light for each of the two polarizations and supplies two phase components that are orthogonal to each other to two PIN-PDs 22. Specifically, the two phase components for one polarization are supplied to the PIN-PDs 22-1 and 22-2 and the two phase components for the other polarization are supplied to the PIN-PDs 22-3 and 22-4.
The operations of the PIN-PD 22, the TIA 23, and the AGC 24 are similar to those in FIG. 17. Each ADC 25 samples an electrical signal supplied from the corresponding AGC 24 in synchronization with a sampling clock signal to generate a digital data signal. Each DSP 26 uses the data signal supplied from the corresponding ADC 25 to perform signal processing.
For example, a flash ADC capable of realizing high-speed processing is used in such a coherent digital optical receiver. The flash ADC is disclosed in, for example, Young-Chan JANG et al., “An 8-GS/s 4-Bit 340 mW CMOS Time Interleaved Flash Analog-to-Digital Converter”, IEICE TRANS. FUNDAMENTALS, VOL.E87-A, NO.2 February 2004, pp.350-356.
The digital optical receiver in the related art described above has the following problems.
The digital optical receiver adopting the phase modulation for the high-speed optical transmission, as in the example in FIG. 18, processes phase components in the elements from the PIN-PD to the DSP in parallel. Accordingly, it is necessary to provide the electrical amplifiers including the TIA and the AGC of a number corresponding to the number of parallel processings and, thus, a nonnegligible increase in the circuit size and the power consumption may be caused.
Furthermore, the provision of the optical hybrid causes an increase in the insertion loss, compared with an optical receiver that adopts Non Return to Zero (NRZ) and that has a bit rate of 10 Gbits/s. In addition, an avalanche photodiode (APD) is not utilized, unlike the optical receiver of 10 Gbits/s.
In consideration of the above differences, it is preferable to provide an optical preamplifier upstream of the digital optical receiver. In such a case, it is expected that an optical power higher than that in the optical receivers in the related art be input into the PIN-PD. If priority is given to a reduction in the circuit size and the power consumption with taking the above advantage, a configuration in which the TIA and the AGC having higher gains are omitted may be proposed.
FIG. 19 illustrates a configuration example of such a coherent digital optical receiver. Referring to FIG. 19, the digital optical receiver includes an optical hybrid 31, PIN-PDs 32-1 to 32-4, ADCs 33-1 to 33-4, and DSPs 34-1 to 34-4. Comparison with the configuration in FIG. 18 indicates that the TIA and the AGC are omitted in the configuration in FIG. 19.
However, since a signal output from each PIN-PD 32 is directly supplied to the corresponding ADC 33 in the configuration in FIG. 19, it is not possible to control the amplitude of the signal input into the ADC 33 in accordance with the power of the optical signal that is received.
FIG. 20 illustrates a configuration example of a flash ADC used in a digital optical receiver. Referring to FIG. 20, the ADC includes clocked comparators 41-1 to 41-4 that are arranged in parallel. Each clocked comparator 41-i (i is equal to any of one to four) compares an analog signal DATA with a reference voltage refi in synchronization with a clock signal CLOCK. If the comparison indicates that the level of the analog signal DATA is higher than the reference voltage refi, the clocked comparator 41-i outputs a high level (H). The clocked comparator 41-i otherwise outputs a low level (L). As a result, parallel data signals in synchronization with the clock signal CLOCK are generated.
FIG. 21 illustrates a configuration example of another flash ADC. Referring to FIG. 21, the ADC includes clocked comparators 41-1 to 41-4 that are arranged in parallel and resistors 42-1 to 42-3. The resistors 42-1 to 42-3 perform resistance division on a reference voltage REFERENCE to generate a reference voltage to be input into each clocked comparator 41-i. The operation of the clocked comparators 41-1 to 41-4 is similar to that in FIG. 20.
The ADCc illustrated in FIGS. 20 and 21 each have a configuration in which the multiple clocked comparators are arranged in parallel. The clocked comparators use different reference voltages to output the comparison results in order to perform the analog-to-digital conversion. Accordingly, the resolution of the analog-to-digital conversion depends on the number of comparators that are arranged in parallel and an increase in the number of the comparators may cause an increase in the power consumption.
As described above with reference to FIG. 19, it is necessary to arrange the multiple high-speed ADCs in parallel in the digital optical receiver. However, it is also necessary to reduce the power consumption as much as possible in terms of the function of an optical transceiver related to an optical receiver and transmitter.
FIGS. 22 and 23 each illustrate an example of the relationship between reference voltage L0 to L6 of an ADC and an analog signal that is input into the ADC.
If the AGC upstream of the ADC is omitted, the effective resolution of the ADC is reduced because the amplitude of an analog signal that is input is decreased, as illustrated by an arrow 51 in FIG. 22. In contrast, upon reception of an analog signal having an amplitude larger than estimated, as illustrated by an arrow 52 in FIG. 23, a signal output from the ADC may not follow the input analog signal and part of information may be lost.
In order to resolve the above problem, clocked comparators may be excessively provided in accordance with an estimated variation in amplitude of an input signal. However, the power consumption may undesirably be increased in such a case.